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Project Window
add constant string
Add constant to the active project.
add top topname library libname [project projname]
Adds design unit ‘topname’ to the active projects list of design
tops.
add [before | after projname] dependent projname1
Adds project ‘projname1’ to the active projects dependency list.
The command has an option to place the project before or after
‘projname’.
add filelist filename
File filename contains a list of Verilog or VHDL source files that
are added to the active project.
add setup setupdir
Directory setupdir contains a synopsys_sim.setup file that is read
into the active project. Adds constants, and both VHDL and Verilog
libraries to the project.
add constant name value
Adds a constant and value to the active project. The constant is
written to the synopsys_sim.setup file created by the Project
window.
analyze project
Analyzes active project and each dependent project only if each
project needs to be analyzed.
analyze all
Unconditionally analyzes the active project and all dependent
projects.
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