Encore SIM EDITOR SOFTWARE User's Guide download pdf (Page 429)

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101

19-3

Viewing OpenVera Assertions

• Tests Verilog, VHDL, and mixed-HDL designs using the VCS and

Scirocco simulators.

• Automatically tests and reports results on all defined sequences.

You just write the definitions.

• Produces results that can be viewed with VirSim.

• Can be monitored and controlled as part of a Vera testbench.

How Sequences Are Tested

Testing starts with a temporal assertion file, which contains the

descriptions of the sequences and instructions for how they should

be tested. OpenVera Assertions is designed to resemble Verilog with

similar data types, operators, and lexical conventions.

Example 19-1 shows an example temporal assertion file. It tests for

a simple sequence of values (4, 6, 9, 3) on the device’s outp bus.

Example 19-1 Temporal Assertion File, cnt.ova

/* Define a unit with expressions and assertions (or select

one from the Checker Library).

unit 4step

#(parameter integer s0 = 0) // Define parameters

(logic clk, logic [7:0] result); // Define ports

// Define a clock to synchronize attempts:

clock posedge (clk)

{

// Define expressions:

event t_0 : (result == s0);

event t_1 : (result == 6);

event t_2 : (result == 9);

event t_3 : (result == 3);

event t_normal_s: t_0 #1 t_1 #1 t_2 #1 t_3;

}

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