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VirSim Overview
• A Logic Browser to clearly present design connectivity: structural
and behavioral, fanins and fanouts, values and delay information
included.
• A Source Window in which to view, execute or debug the complete
source.
• Data from different runs or designs can be viewed in the same
window.
• Windows can be synchronized to the same or different times.
• Execution can be backward or forward in time.
• View stand-alone compiled sources to debug Verilog source, even
before your fist simulation.
Performance and memory usage are optimized to handle large
designs
• Data files use binary VCD+ format for compactness and high-
performance access. These can be up to 100 times smaller than
VCD files and contain more information.
• Memory is used efficiently during simulation and analysis.
• Algorithms are optimized for fast loading of data and screen
updates.
Support of multiple languages, platforms, and simulators.
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