Encore SIM EDITOR SOFTWARE User's Guide download pdf (Page 428)

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Viewing OpenVera Assertions

Introducing OpenVera Assertions

OpenVera Assertions (OVA) provides a clear, easy way to describe

sequences of events and facilities to test for their occurrence. With

clear definitions and less code, testbench design is faster and easier.

And you can be confident that you are testing the right sequences in

the right way.

OpenVera Assertions is a declarative method that is much more

concise and easier to read than the procedural descriptions provided

by hardware description languages such as Verilog. With OpenVera

Assertions:

• Descriptions can range from the most simple to the most complex

logical and conditional combinations.

• Sequences can specify precise timing or a range of times.

• Descriptions can be associated with specified modules and

module instances.

• Descriptions can be grouped as a library for repeated use.

OpenVera Assertions includes a Checker Library of commonly

used descriptions.

Built-in Test Facilities and Functions

OpenVera Assertions has built-in test facilities to minimize the amount

of code that you need to write. In addition, OpenVera Assertions works

seamlessly with other Synopsys tools to form a complete verification

environment. OpenVera Assertions:

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