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Event Origin
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Event Origin 1
The VirSim Event Origin feature (Verilog only) can help you to obtain
precise information about the origin of a signal value change at a
specific time. VirSim can display signals from all levels of a design
hierarchy, including signals named differently but logically equivalent
by connection through a module port. Whatever the signal data type
and location in the hierarchy, there is a root cause for every signal
change, referred to as its event origin.
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