Encore SIM EDITOR SOFTWARE User's Guide download pdf (Page 201)

100

101

6-17

Logic Browse

Expressions Example

The following example illustrates the types of complex port

expressions that are legal in the Verilog HDL. Consider the following

Verilog code:

module mid ({i1,i2}, {o1, o2[3:2], o2[0]});

input [4:0] i1;

input [2:0] i2;

output o1;

output [3:0] o2;

buf g0 (o2[3], i1[4]);

not g1 (o2[2], i1[3]);

buf g2 (o2[1], i1[2]);

not g3 (o2[0], i1[0]);

buf g4 (o1, &i2);

endmodule

module top;

wire y, z;

wire [1:0] netv1;

reg [1:0] a, b;

initial

begin

$vcdplusdeltacycleon;

$vcdpluson;

$vcdplustraceon;

repeat (10) #10 {a,b} = $random;

end

mid m0 ({a ^ b, 2'b01, a, b}, {z,y});

and andNet2 (z, y, a[0]);

assign netv1 = {y | a[0], y & a[0]};

endmodule

Assume that we have compiled this design and we view the focus

top.a in the Logic Browser. The Logic Browser view is shown in

Figure

6-4, Connection Dialog Example.

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