13-3
Building Buses
Bus Builder Dialog
Figure 13-1, Bus Builder Dialog, shows the major areas of the Bus
Builder Dialog.
Figure 13-1 Bus Builder Dialog
Name
Buses can be named any legal name for the language (e.g., Verilog,
VHDL). The bit ranges should not be specified as part of the name
as they are added automatically (like any other vector). If no name is
specified, by default buses are numbered consecutively within each
design file (Bus1 through BusN).
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