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Project Window
What is a Project?
A project contains VHDL and Verilog source file paths, libraries that
receive analyzer output, references to other projects that might need
to be analyzed when the project is analyzed, and names of design
units that are used as design tops for elaboration and simulation.
VHDL and Verilog source files are added to a project. The project is
analyzed and analyze errors are corrected. The project is then
elaborated and simulated. To troubleshoot the design, open individual
Virsim Windows.
Multiple projects can be used to partition a design into manageable
units and to build multiple libraries for a design.
What is a Design Top?
A design top is an entity, configuration or package declaration. The
active design top is the design unit that will be passed to the Analyze
or Simulate command.
To add a design top to a project first analyze the project, and then
view the contents of the library containing analyzer output (right-click
on the library name). The view displays entities, package
declarations, and configurations. Use the View popup menu to add a
design top to the project.
- VirSim User Guide 1
- VirSim 3
- User Guide 3
- Contents 5
- About this Manual FIX ME! 23
- Licensing 24
- Audience 24
- Platforms 25
- Other Sources of Information 25
- X Resources 26
- SOLV-IT! Online Help 27
- Customer Support 27
- About this Manual 28
- VirSim Overview 1 29
- Operation Modes 30
- Advantages of VirSim 31
- VirSim Overview 32
- Key Terms and Concepts 33
- OSF/Motif™ environment 34
- VirSim Windows 35
- VirSim Navigation 44
- Selecting Signals 46
- Drag-and-drop Operation 47
- Linking Windows 49
- Figure 1-9 Linking Window 50
- Accelerator Keys 51
- Operation Accelerator 52
- HB WW SW LB RW IW 52
- Starting VirSim 1 55
- Starting VirSim 56
- +cfgfile+<filename> 57
- +vslogfile+<filename> 57
- <signal>) 57
- +cfgfile+default.cfg 60
- VHDL Command Line Syntax 62
- Figure 2-2 Command Line 66
- Opening the Open File Dialog 71
- Figure 2-3 Open File Dialog 72
- Open Files 72
- Opening a Single History File 76
- Closing History Files 77
- Reopening History Files 79
- Saving a Configuration File 81
- Loading a Configuration File 82
- Configuration File Format 83
- Nested Configuration Files 84
- Loading Sources 85
- Hierarchy Browser 1 89
- Selecting a Design 91
- Choosing View Options 92
- Hierarchy Browse 93
- Navigating the Hierarchy 94
- Adding Signals to a Group 97
- Hierarchy Browser 100
- Menu Bar 101
- File Menu 101
- Edit Menu 102
- Display Menu 102
- View Menu 103
- Waveform Window 1 105
- Waveform Window 106
- Signal Value Pane 108
- Waveform Pane 110
- Cursor Pane 111
- Status Bar 112
- Selecting and Viewing Signals 113
- Adding and Reordering Signals 113
- User Defined Buses 117
- Zooming Waveforms 118
- Note: 121
- Delta Cycles 123
- Expand and Collapse Times 124
- View Delta Cycles 125
- Advanced Features 127
- Expressions 128
- Creating Breakpoint Groups 128
- Changing the Display Format 133
- Selecting Drawing Mode 134
- Modifying Waveform Height 135
- Additional Features 140
- Printing Waveforms 142
- Printing a Time Range 143
- Specifying a Printer Name 145
- Printing to Postscript 145
- Toolbar and Menu Reference 147
- Context Sensitive Menus 150
- Zoom Menu 156
- Source Window 1 159
- Execution Pane 161
- Source Text Pane 162
- Control Pane 163
- Table 5-2 Control Pane 164
- Source Window 165
- Navigate and View a Design 166
- Edit the Correct Design File 167
- Follow Source Execution 169
- Control Source Execution 169
- Using Breakpoints 169
- Set Breakpoints 169
- Clear Breakpoints 170
- Run to Breakpoints 170
- Using Instance Groups 171
- Define Markers 174
- Capture Line Data 175
- Descend Instance 179
- Go to Parent 179
- Logic Browser 1 185
- Introducing the Logic Browser 186
- Getting Started 188
- Viewing Graphic Objects 189
- Logic Browser 190
- Logic Browse 191
- Navigating a Design 194
- Using Event Origin 198
- Using the Connection Dialog 198
- Expressions Example 201
- Changing the Display 203
- Toolbar and Menu Reference 205
- Next Selected 206
- Signals Change 206
- Logic Browser CSM 207
- Prev/Next Change 208
- Load View NL 208
- Edit At Definition 208
- Module Instance CSM 209
- Port Instance CSM 210
- Event Origin 211
- Load Value 211
- View Connection 211
- Selected Net CSM 212
- Register Window 1 217
- What is a View? 218
- Which Signals are Loaded? 219
- Edit Views 220
- Undo Command 221
- Display Unique Events 222
- Set Time Scale 222
- Align Objects 223
- Distribute Objects 223
- Register Window 226
- Signal Properties CSM 228
- Select All 230
- Graphics Menu 234
- Interactive Window 1 237
- History Pane 238
- Command Prompt 238
- User-Defined Buttons 239
- Simulator Controls 239
- Step Control 239
- Scope Control 240
- Time Display 240
- Window Status 241
- Interactive Window 242
- Simulation 243
- Controlling the Simulator 245
- Breakpoint Durations 246
- Expression Breakpoints 247
- Line Breakpoints 250
- Default Buttons Files 252
- Creating User-Defined Buttons 253
- Defining a Button 254
- Selection Substitution 255
- File Commands 257
- Edit Commands 257
- Sim Commands 258
- Project Window 1 261
- Project Window 262
- What is a Workspace? 263
- What is a Project? 264
- What is a Design Top? 264
- Workspace Pane 265
- View Pane 269
- Project Folder View 270
- Design Top Folder View 271
- Source File Folder View 272
- Dependency Folder View 274
- Library Folder View 275
- New VHDL Library 277
- New Verilog Library Work 277
- New Verilog Library Other 277
- Library View 278
- Add Top 279
- Edit Source 279
- View Full Detail 279
- Tear Off Windows 280
- Output Pane 280
- Project Menu 285
- Tools Menu 287
- Windows Menu 288
- New Workspace Dialog 289
- Open File Dialog 291
- Add Files Dialog 293
- Select a Directory Dialog 295
- Edit Setup Constants Dialog 296
- New Verilog Library Dialog 298
- Library Name 298
- Path Name 298
- Using the Options Dialog 299
- Options Dialog Buttons 300
- Setting Analyze Options 301
- Setting Elaborate Options 302
- Setting Simulate Options 304
- Setting Verilog Run Options 306
- Commands 308
- Files and Directories 314
- Moving Projects 315
- Using a Makefile 316
- Time Units 1 317
- Display Unit 318
- Time Units 319
- Radices 1 321
- Radix Dialog 323
- Radix Editor 324
- Mapping List Editor 325
- Creating a User-Defined Radix 326
- Event Origin 1 327
- Before Using Event Origin 328
- How to Use Event Origin 329
- Display the Event Origin 331
- Debug with Event Origin 334
- Building Buses 1 337
- Building Buses 338
- Bus Builder Dialog 339
- Markers 1 345
- Marker knownOk set 346
- Markers Dialog 347
- Opening the Marker Dialog 349
- Creating a Marker 349
- Deleting a Marker 349
- Editing a Marker 350
- Setting a Marker 350
- Expressions 1 353
- Expressions Dialog 354
- Entering Signal Names 358
- Creating Expressions 359
- Updating Expressions 360
- Displaying Expressions 361
- Trigger Types 362
- Searching with Expressions 363
- Level Sensitive Searches 364
- Edge-triggered Searches 365
- VirSim Setup 1 367
- Caution: Before You Start 368
- VirSim Platforms 368
- Common Settings 370
- Mouse Button Setting 371
- VirSim Setup 372
- Waveform Window Settings 374
- Source Window Settings 376
- Hierarchy Window Settings 377
- Logic Browser Settings 378
- Register Window Settings 379
- Interactive Window Settings 380
- Settings for X Resources 381
- X Color System 382
- Switching Color Maps 383
- VCD+ (vpd) File Generation 1 385
- Advantages of VCD+ 386
- System Tasks and Functions 387
- $vcdpluson; 388
- $vcdplusoff 389
- $vcdplusautoflushon 390
- $vcdplusautoflushoff 390
- VCD+ (vpd) File Generation 391
- Syntax for Specifying MDAs 392
- Examples 394
- Note: Unlimited dimensions 395
- Starting bound: 396
- Ending bound: 396
- mem01[2][5][8] 400
- Selected element: 400
- $vcdplusmemorydump Task 401
- Execution Data 401
- Execution 402
- Source Statement System Tasks 403
- $vcdplustraceon 403
- Simulator Run-Time Options 408
- VCD+ Methodology 411
- C1> sigon_instreg; 414
- VCD+ On/Off PLI Rules 415
- Performance Tips 416
- Translating VCD and VCD+ 1 419
- <vpd_file> 420
- EVCD Options 421
- Translating VCD and VCD+ 422
- VCD file in ASCII format 423
- VHDL Mapping 424
- Viewing OpenVera Assertions 1 427
- Viewing OpenVera Assertions 428
- How Sequences Are Tested 429
- Viewing OVA Results in VirSim 431
- Waveform Defaults 2 435
- Waveform Defaults 436
- Waveform Style: VHDL Defaults 438
- Chapter 16 439
- Table A-2 VHDL Defaults 439
- Waveform Style: EPIC Defaults 440
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