Encore SIM EDITOR SOFTWARE User's Guide download pdf (Page 412)

100

101

17-28

VCD+ (vpd) File Generation

Advantages of Separating Simulation from Analysis

When a problem is debugged, traditionally, interactive debugging has

required a user to occupy one simulator license while simulating,

thinking, resimulating, thinking...

Simulating once and efficiently storing as much data as possible

allows for a more efficient debug methodology:

• The simulator is used once and then released to others.

• The analysis tool can go both forwards and backwards in time and

analyze the complete set of data.

• The same set of data can be used by multiple engineers to debug

one or more problems in parallel.

Conceptual Example of Using Verilog VCD+ System

Tasks

The example in Figure 17-8, Example Definition of VCD+ Signal

Capture (Recording), shows the entry of the $vcdplus system tasks

in Module B scope. The dump saves all the variables in Module B

from time 100 to 300, all variables in module C from time 200 to 500,

and a single variable in module D1.clk from time 600 to 900. Zero

delay glitch detection is on while value change data is being recorded

throughout the simulation. Delta cycle information is stored starting

at the first value change that occurs after time 200 and ending after

the last value change during time 300. At time 700 a unique event is

added to signal D.clk.

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