19-4
Viewing OpenVera Assertions
// Define an assertion:
assert c_normal_s : check(t_normal_s, "Missed a step.");
endunit
/* Bind the unit to one or more instances in the design.
*/
// bind module cnt : // All instances of cnt or
bind instances cnt_top.dut : // one instance.
4step start_4 // Name the unit instance.
#(4) // Specify parameters.
(m_clk, outp); // Specify ports.
When the temporal assertion file is compiled and run with a simulator,
the assertions are continuously tested for the duration of the
simulation. New attempts to match each assertion to the simulation’s
values are started with every cycle of the assertion’s associated clock.
Each attempt continues until it either fails to match or succeeds in
matching the complete expression. See
Figure 19-2. The up arrow
at clock tick 7 indicates a match that started at tick 4. The down arrows
are failures. The failure or success of each attempt is logged to a file
that can be reviewed later.
Figure 19-2 Assertion Attempts for cnt.ova
A Vera testbench can monitor and control the testing. Using built-in
object classes, you can stop and start attempts to match the selected
assertion; monitor attempts, failures, and successes; and
synchronize the testbench with the testing process.
1234567891011121314posedge m_clk
outp
c_normal_s
06 04 0408 06 09 03 0d 0e 04 06 09 06
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