15-4
Expressions
File
Specifies the file designator for the file associated with signal name.
File designators are selected from the pull-down menu next to the
File field. Not all file types support expressions. The File field displays
only those open files that support expressions. If the Trigger or
Expression field contains the file designator, the File field is ignored
(see Scope below).
Scope
Specifies a scope from which signal names in the Trigger and
Expression fields are referenced. If the Trigger and Expression fields
include the file designator and full hierarchy names of the scope, the
Scope field is ignored.
For example, the following expression does not require a file
designator and scope because it includes the file designator and full
hierarchy name:
Verilog:
($V1$test.risc1.alu_out[7:0])===($V1$test.risc1.accum[7:0])
VHDL:
$V1$test/risc1/alu_out(7 Downto 0)===
$V1$test/risc1/accum(7 Downto 0)
The following expression requires a file designator and scope
because it does not include the file designator and full hierarchy
name:
Verilog:
(alu_out[7:0])===(accum[7:0])
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