Encore SIM EDITOR SOFTWARE User's Guide download pdf (Page 357)

100

101

15-5

Expressions

VHDL

alu_out(7 Downto 0)===accum(7 Downto 0)

When the expression does not include the full hierarchy name, VirSim

looks for all signals in the referenced scope. If you drag in a signal

from another window, VirSim automatically adds the file designator

and full hierarchy name to the expression.

Verilog Trigger

The trigger is edge-sensitive. The trigger can use two Verilog edge

operators: posedge and negedge or, if the trigger uses just the signal

name, any transition of that signal satisfies the expression. If it uses

posedge, then only the rising transitions (x->1, 0->1, z->1) satisfy

the expression. If it uses negedge, then only the falling transitions

(x->0, 1->0, 1->z) satisfy the expression.

VHDL Trigger

The trigger is edge-sensitive. The trigger can use VHDL signal

attribute S’event. For example, clk’event and clk==1--rising

edge clk, and clk’event and clk==0--following edge clk. If the

trigger uses just the signal name, any transition of the signal satisfies

the expression.

Expression

The expression is level-sensitive. To enter an expression, type the

expression, drag and drop in signals, and insert operators. For signals

that you drag and drop, the file designator and full hierarchy name

are automatically inserted in the expression.

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Encore SIM EDITOR SOFTWARE User's Guide Page 357

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